Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

One- and two-dimensional N-qubit systems in capacitively coupled quantum dots

Coulomb blockade effects in capacitively coupled quantum dots can be utilized for constructing an N-qubit system with antiferromagnetic Ising interactions. Starting from the tunneling Hamiltonian, we theoretically show that the Hamiltonian for a weakly coupled quantum-dot array is reduced to that for nuclear magnetic resonance (NMR) spectroscopy. Quantum operations are carried out by applying only electrical pulse sequences. Thus various error-correction methods developed in NMR spectroscopy and NMR quantum computers are applicable without using magnetic fields. A possible measurement scheme in an N-qubit system is quantitatively discussed.Comment: 5 pages, revtex, 3 figures, to appear in Phys. Rev.

Simulation study of ballistic spin-MOSFET devices with ferromagnetic channels based on some Heusler and oxide compounds

Newly emerged materials from the family of Heuslers and complex oxides exhibit finite bandgaps and ferromagnetic behavior with Curie temperatures much higher than even room temperature. In this work, using the semiclassical top-of-the-barrier FET model, we explore the operation of a spin-MOSFET that utilizes such ferromagnetic semiconductors as channel materials, in addition to ferromagnetic source/drain contacts. Such a device could retain the spin polarization of injected electrons in the channel, the loss of which limits the operation of traditional spin transistors with non-ferromagnetic channels. We examine the operation of four material systems that are currently considered some of the most prominent known ferromagnetic semiconductors: three Heusler-type alloys (Mn2CoAl, CrVZrAl, and CoVZrAl) and one from the oxide family (NiFe2O4). We describe their band structures by using data from DFT (Density Functional Theory) calculations. We investigate under which conditions high spin polarization and significant ION/IOFF ratio, two essential requirements for the spin-MOSFET operation, are both achieved. We show that these particular Heusler channels, in their bulk form, do not have adequate bandgap to provide high ION/IOFF ratios and have small magnetoconductance compared to state-of-the-art devices. However, with confinement into ultra-narrow sizes down to a few nanometers, and by engineering their spin dependent contact resistances, they could prove promising channel materials for the realization of spin-MOSFET transistor devices that offer combined logic and memory functionalities. Although the main compounds of interest in this paper are Mn2CoAl, CrVZrAl, CoVZrAl, and NiFe2O4 alone, we expect that the insight we provide is relevant to other classes of such materials as well

Designing With 3D SOI CMOS

This paper presents a new three-dimensional CMOS-SOI technology and discusses design issues for it. In this technology the P-channel devices are stacked over the N-channel ones. All gates are 0.1µm length. New design constraints are introduced. Consequently, new design methodologies have to be developed in order to fully take advantage of the outstanding features of 3D integration like for example the reduced length of interconnections. INTRODUCTIO

EUREKA Verbundprojekt PROMETHEUS Teilprojekt PRO-CHIP. Schlussbericht fuer die Definitionsphase

TIB Hannover: FR 3865+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

ASIC-Arbeitsgruppe Neurologik fuer industrielle Mess-, Sensor- und Regelanwendung (JESSI AE23) Abschlussbericht

The application of new microsystem technologies offers a lot of advantages in effectiveness and functionality when comparing solutions in the field of monitoring or industrial control using them with those based on conventional principles. Neural controllers can be used advantageously, either if the data to be processed are characterized by nonlinear functions, or algorithms cannot be defined or the setup of such an algorithm is very complicated. Objective of the the project was the development of digital, multi-usable neural hardware modules. Participants were the Institut fuer Mikroelektronic Stuttgart and GEMAC Chemnitz being responsible for the development and a working group of SMEs from Baden-Wuerttemberg and Saxony being potential users of the hardware results. The working group members got a version of the neural network simulation tool NNSIM for own neural projects which was adapted to their needs. The companies were assisted by IMS and GEMAC in the form of training courses and project-oriented consultations. The main deliverables were two neural chips for different applications: One ASIC with a full integrated neural network (including weight memories) for high-speed applications and small up to medium number of inputs, e.g. for process control applications ('SIOP2-ASIC'), and another one with a higher number of inputs, an internal high-performance processing unit consisting of 4 parallel ALUs and external weight memories, e.g. for image processing ('PIOS'). The working group members were actively involved in the system specification of the chips. For each of the ASICs application boards were designed and manufactured in order have an instrument for the evaluation of the developed neural networks. E.g., the SIOP2 board contains a SCSI2 interface, D/A converter as well as a direct and a serial interface. Based on the layout-optimized modules, each of the working group members can design its own, application adapted and optimized ASIC. Alternatively, the standard configurations of the existing ASICs can be used. (orig.)Available from TIB Hannover: F98B951+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman